document ver. 4.1 deutron electronics corp. data sheet 2g bits ddr3 sdram pdj2108debg (256m words 8 bits) PDJ2116DEBG (128m words 16 bits) specifications ? density: 2g bits ? organization: ? 32m words 8 bits 8 banks (p dj2108debg) ? 16m words 16 bits 8 banks (edj2116debg) ? package: ? 78-ball fbga (p dj2108debg) ? 96-ball fbga (p dj2116debg) ? lead-free (rohs compliant) and halogen-free ? power supply: vdd, vddq = 1.5v 0.075v ? data rate ? 1600mbps/1333mbps (max.) ? 1kb page size (p dj2108debg) ? row address: a0 to a14 ? column address: a0 to a9 ? 2kb page size (p dj2116debg) ? row address: a0 to a13 ? column address: a0 to a9 ? eight internal banks for concurrent operation ? interface: sstl_15 ? burst lengths (bl): 8 and 4 with burst chop (bc) ? burst type (bt): ? sequential (8, 4 with bc) ? interleave (8, 4 with bc) ? /cas latency (cl): 6, 7, 8, 9, 10, 11 ? /cas write latency (cwl): 5, 6, 7, 8 ? precharge: auto precharge option for each burst access ? driver strength: rzq/7, rzq/6, rzq/5 (rzq = 240 ) ? refresh: auto-refresh, self-refresh ? refresh cycles ? average refresh period 7.8 s at 0 c tc + 85c 3.9 s at + 85c < tc + 95c ? operating case temperature range ? tc = 0 c to +95 c features ? double-data-rate architecture: two data transfers per clock cycle ? the high-speed data transfer is realized by the 8 bits prefetch pipelined architecture ? bi-directional differential data strobe (dqs and /dqs) is transmitted/received with data for capturing data at the receiver ? dqs is edge-aligned with data for reads; center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? data mask (dm) for write data ? posted /cas by programmable additive latency for better command and data bus efficiency ? on-die termination (odt) for better signal quality ? synchronous odt ? dynamic odt ? asynchronous odt ? multi purpose register (mpr) for pre-defined pattern read out ? zq calibration for dq drive and odt ? /reset pin for power-up sequence and reset function ? srt range: ? normal/extended ? programmable output driver impedance control ? seamless bl4 access with bank-grouping
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